Principal, IO Design Engineering

The role involves designing, optimizing, and verifying high-speed IO and clocking circuits for DRAM memory products. Responsibilities include developing simulation methodologies and collaborating with process integration teams to enhance circuit performance on new process nodes.

Responsibilities

• Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products
• Apply proven high-speed circuit design techniques and enhance critical performance evaluation of the IO data path and clocking path at circuit level
• Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level
• Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities
• Collaborate with process integration and transistor modeling teams on Micron's next groundbreaking process node

Requirements

• Minimum MSEE + 10 years or BSEE + 12 years of industry experience in analog and mixed-signal circuit design
• Proficiency with UNIX and CADENCE design environment (simulation, schematic entry, SPF extraction)
• Understanding of device physics and basic CMOS processing techniques
• Ability to supervise layout work and understand good layout practices for high-speed circuits to minimize parasitic impacts
• Strong communication skills with the ability to convey sophisticated technical concepts to other design peers both verbally and written

Benefits

• Choice of medical, dental and vision plans
• Paid family leave
• Robust paid time-off program and paid holidays

Key Skills