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FPGA / RTL Design Engineering Intern (VHDL, Verilog, SystemVerilog) – Barcelona
Keysight Technologies, Inc. 🇪🇸 Barcelona, Catalonia, Spain
Design and implement RTL for FPGA-based systems using VHDL, Verilog, or SystemVerilog while developing testbenches for functional verification. Integrate, debug, and validate designs on real FPGA hardware and collaborate on digital signal processing and system integration.
Responsibilities
- Design and implement RTL for FPGA-based systems using VHDL, Verilog, or SystemVerilog while developing testbenches for functional verification. Integrate, debug, and validate designs on real FPGA hardware and collaborate on digital signal processing and system integration.
Requirements
- Candidates must be currently enrolled in a Bachelor’s or Master’s degree in a relevant engineering field and be able to sign an internship agreement. Applicants require hands-on experience with FPGA development, RTL coding, and simulation tools, along with fluent English proficiency.
Key Skills
About Keysight Technologies, Inc.
At Keysight, we empower innovators to bring world-changing technologies to life. Since our beginnings in a Silicon Valley garage, we’ve understood that innovation is a journey. You need a collaborative advisor who’ll provide expertise and tailored solutions to take you from concept to reality. Push the boundaries of engineering and deliver the best product experiences with our technologies, measurement expertise, and tailored solutions, built from a foundation of co-innovation with industry ecosystem leaders. Gather insights, sooner, to build and go-to-market with confidence. Keysight (NYSE: KEYS) serves technology innovators as a mission-critical design enablement partner for the world’s most complex engineering challenges. By connecting market-leading design, emulation, and test solutions across the full lifecycle, Keysight helps engineering teams accelerate innovation, reduce risk, and bring new technologies to market faster. Customers across AI infrastructure, communications, ind
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