Senior ASIC Physical Design Engineering Technical Lead

Lead full-chip RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, timing analysis, power integrity, equivalence checks, and performance and die-size optimization. Improve design flows and methodologies, guide clock-tree and timing-closure strategies, coordinate with cross-functional teams and EDA vendors, and support ECO implementation and STA automation.

Responsibilities

• Lead full-chip RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, timing analysis, power integrity, equivalence checks, and performance and die-size optimization. Improve design flows and methodologies, guide clock-tree and timing-closure strategies, coordinate with cross-functional teams and EDA vendors, and support ECO implementation and STA automation.

Requirements

• Requires a bachelor's degree in electrical engineering with 12+ years of physical-design experience, a master's degree with 8+ years, or a PhD with 5+ years, along with full-chip experience and tapeouts at 7nm, 5nm, 3nm, or smaller. Candidates should have experience with RTL-to-GDSII flows and tools such as Innovus, PrimeTime or Tempus, RedHawk or Voltus, and Calibre; hierarchical design, timing closure, power integrity, floorplanning, clock design, and scripting are preferred.

Benefits

• Medical Insurance
• Dental Insurance
• Vision Insurance
• 401(k) With Matching Contributions
• Paid Parental Leave
• Short-Term Disability Coverage
• Long-Term Disability Coverage
• Life Insurance
• Paid Holidays
• Floating Holiday
• Birthday Leave
• Year-End Holiday Shutdown
• Personal Wellness Leave
• Paid Vacation
• Sick Leave
• Volunteer Leave
• Annual Bonuses
• Restricted Stock Units

Key Skills