Senior ASIC Physical Design Engineering Technical Lead

Lead RTL-to-GDSII implementation and optimize performance, die size, timing, and power integrity across full-chip designs. Improve design flows and methodologies, guide clock-tree strategies, drive STA and sign-off convergence, implement ECOs, and collaborate with RTL, DFT, implementation, EDA vendors, and tool teams.

Responsibilities

• Lead RTL-to-GDSII implementation and optimize performance, die size, timing, and power integrity across full-chip designs. Improve design flows and methodologies, guide clock-tree strategies, drive STA and sign-off convergence, implement ECOs, and collaborate with RTL, DFT, implementation, EDA vendors, and tool teams.

Requirements

• Requires a bachelor's degree in electrical engineering with 12+ years of physical design experience, a master's degree with 8+ years, or a PhD with 5+ years. Candidates must have full-chip experience, RTL-to-GDSII tapeouts at 7nm/5nm/3nm or below, and experience with tools such as Innovus, PrimeTime or Tempus, RedHawk or Voltus, and Calibre.

Benefits

• Medical Insurance
• Dental Insurance
• Vision Insurance
• 401(k) With Matching Contributions
• Paid Parental Leave
• Short-Term Disability Coverage
• Long-Term Disability Coverage
• Life Insurance
• Restricted Stock Units
• Paid Holidays
• Floating Holiday
• Birthday Leave
• Year-End Holiday Shutdown
• Personal Wellness Days
• Paid Vacation
• Sick Leave
• Family Emergency Leave
• Paid Volunteer Days
• Annual Bonus

Key Skills