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Senior ASIC Physical Design Engineering Technical Lead
Cisco đşđ¸ San Jose, California, United States of America
The role involves managing RTL-to-GDSII implementation, including synthesis, floorplanning, and timing analysis to optimize performance and die size. You will also collaborate with cross-functional teams to enhance design methodologies and execute sign-off processes for complex silicon projects.
Responsibilities
- Manage RTLâtoâGDSII implementation, including synthesis, floorplanning, and timing analysis
- Optimize performance and die size for silicon projects
- Collaborate with crossâfunctional teams to enhance design methodologies
- Execute signâoff processes for complex ASIC projects
- Lead technical reviews and mentor junior designers
Requirements
- Degree in Electrical Engineering
- 5â12 years of physical design experience depending on degree level
- Expertise in fullâchip RTLâtoâGDSII flows
- Proficiency with synthesis, floorplanning, and timing analysis
- Experience with advanced process technologies such as 7nm, 5nm, or 3nm
- Strong knowledge of ASIC design methodology
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) plan
- Cisco matching contribution
- Paid parental leave
- Short-term disability coverage
- Long-term disability coverage
- Basic life insurance
- Restricted stock units
- Paid holidays
- Paid birthday leave
- Year-end holiday shutdown
- Personal wellness days
- Paid vacation time
- Sick time off
- Volunteer time off
Key Skills
About Cisco
Cisco is the worldwide technology leader that is revolutionizing the way organizations connect and protect in the AI era. For more than 40 years, Cisco has securely connected the world. With its industry leading AI-powered solutions and services, Cisco enables its customers, partners and communities to unlock innovation, enhance productivity and strengthen digital resilience. With purpose at its core, Cisco remains committed to creating a more connected and inclusive future for all.
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