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Design Engineering Architect
Cadence Design Systems đŽđł Bengaluru, Bangalore North, India
Optimize and verify signal and power integrity for test-chip packages and evaluation boards, and provide extracted and measured channel models for chip designers. Support customers through design reviews, guidelines, performance simulations, and lab debugging of test chips or customer ASICs.
Responsibilities
- Optimize and verify signal and power integrity for test-chip packages and evaluation boards, and provide extracted and measured channel models for chip designers. Support customers through design reviews, guidelines, performance simulations, and lab debugging of test chips or customer ASICs.
Requirements
- Requires an M.S. or Ph.D. in Electrical Engineering or a similar field and 15 or more years of experience, preferably with high-speed SerDes and PHYs. Candidates should have hands-on lab and extraction-tool experience, IBIS-AMI simulation and measurement-correlation expertise, knowledge of PCB and FCBGA design, and strong communication and problem-solving skills.
Key Skills
About Cadence Design Systems
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadenceâs Intelligent System Design⢠strategy, are essential for the worldâs leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the worldâs top 100 best-managed companies. Cadence solutions offer limitless opportunitiesâlearn more at www.cadence.com.
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