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Physical Design Engineering Director
Astera Labs đ¨đŚ Toronto, Ontario, Canada
Lead and develop the Toronto physical design team, owning block- and top-level implementation of retimer and signal-conditioning ASICs from floorplanning through tapeout and sign-off. Coordinate with cross-functional and global teams, integrate vendor IP, and establish scalable physical design methodologies and quality checks.
Responsibilities
- Lead and develop the Toronto physical design team, owning block- and top-level implementation of retimer and signal-conditioning ASICs from floorplanning through tapeout and sign-off. Coordinate with cross-functional and global teams, integrate vendor IP, and establish scalable physical design methodologies and quality checks.
Requirements
- Requires a bachelor's degree in electrical engineering, computer engineering, or a related field, with a master's preferred, plus 15 or more years of advanced-node SoC physical design experience and at least five years leading teams or projects. Candidates need hands-on expertise across the physical design and sign-off flow, proficiency with Cadence or Synopsys tools, and scripting skills in Tcl, Python, or Perl; high-speed SerDes knowledge is preferred.
Key Skills
About Astera Labs
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labsâ Intelligent Connectivity Platform integrates CXLÂŽ, Ethernet, NVLink⢠Fusion, PCIeÂŽ, and UALink⢠semiconductor-based technologies with the companyâs COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The companyâs custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
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