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Senior Digital Design Manager - High-Speed AI Silicon
Astera Labs 🇺🇸 San Jose, California, United States of America
Lead front-end RTL design for high-performance PCIe, CXL, UAL, and Ethernet devices from architecture through verification, physical design, tape-out, and shipment. Mentor a team of 6–8 engineers, establish design checklists, and collaborate with architecture and system teams to meet schedule and quality targets.
Responsibilities
- Lead front-end RTL design for high-performance PCIe, CXL, UAL, and Ethernet devices from architecture through verification, physical design, tape-out, and shipment. Mentor a team of 6–8 engineers, establish design checklists, and collaborate with architecture and system teams to meet schedule and quality targets.
Requirements
- The role calls for senior-level digital design leadership and experience guiding RTL development across the silicon design lifecycle. It also requires the ability to mentor engineers and work with architecture and system teams to translate requirements into robust implementations.
Key Skills
About Astera Labs
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink™ Fusion, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
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