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Physical Design Engineering Lead
Highbrow Technology Inc 🇺🇸 San Jose, California, United States of America
Lead hands-on ASIC physical design and RTL-to-GDSII implementation, from floorplanning through placement, clock tree synthesis, routing, timing closure, and physical signoff. Collaborate with RTL, STA, DFT, verification, and other teams to optimize implementation and improve physical design flows and methodologies.
Responsibilities
- Lead hands-on ASIC physical design and RTL-to-GDSII implementation, from floorplanning through placement, clock tree synthesis, routing, timing closure, and physical signoff. Collaborate with RTL, STA, DFT, verification, and other teams to optimize implementation and improve physical design flows and methodologies.
Requirements
- Candidates should have relevant physical design experience, a strong understanding of the netlist-to-GDSII flow, and hands-on expertise in implementation, timing analysis, and signoff. A bachelor's or master's degree in electrical engineering, computer engineering, or a related field is required, along with strong problem-solving, debugging, communication, and teamwork skills.
Key Skills
About Highbrow Technology Inc
Highbrow Technology Inc. is a global technology solutions provider, currently assisting clients in the Generative AI (GenAI) space. Our expertise includes Prompt Engineering, LLM Training, and custom AI model training tailored to meet customer-specific data needs, all while ensuring compliance with PII,PCI and HIPAA regulations. We work across various industries to help clients safely integrate AI into their operations. Beyond GenAI, we have established Centers of Excellence (COE) in leading technologies like Workday, SAP, PEGA, Salesforce, ServiceNow, as well as Data Engineering, Cloud Solutions, Security, and Infrastructure. With a strong presence in both the USA and India, we are rapidly expanding into additional geographic regions. For more details, please reach out to our team at hr@highbrowtechnology.com.
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