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Silicon Design Manager, RTL Machine Learning, Accelerator Design
Google đşđ¸ Sunnyvale, California, United States of America
Lead, mentor, and manage a team of RTL Design Engineers focused on IP development for compute cores. Collaborate with cross-functional teams to define architecture, optimize power and performance, and drive design methodology improvements.
Responsibilities
- Lead, mentor, and manage a team of RTL Design Engineers focused on IP development for compute cores. Collaborate with cross-functional teams to define architecture, optimize power and performance, and drive design methodology improvements.
Requirements
- Requires a bachelor's degree in a relevant engineering field and at least 10 years of experience in chip and ASIC digital design. Candidates must possess strong expertise in SystemVerilog, computer architecture, and prior experience in people management.
Benefits
- Bonus
- Equity
- Health Insurance
Key Skills
About Google
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone. Check out our career opportunities at goo.gle/3DLEokh
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