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CPU Cache Subsystem Senior Design Manager

Google 🇺🇸 Austin, Texas, United States of America

$240,000 - $333,000 Full-time Senior

Lead and manage a front-end design team to develop micro-architecture and RTL for next-generation CPU subsystems. Collaborate with cross-functional teams including architecture, verification, and physical design to ensure high-quality productization and PPA goals.

Responsibilities

  • Lead and manage a front-end design team to develop micro-architecture and RTL for next-generation CPU subsystems. Collaborate with cross-functional teams including architecture, verification, and physical design to ensure high-quality productization and PPA goals.

Requirements

  • Requires a bachelor's degree in Electrical Engineering or Computer Science and at least 15 years of experience in CPU design. Candidates must have expertise in load-store unit logic, cache subsystems, and front-end quality checks.

Benefits

  • Bonus
  • Equity
  • Health Insurance

Key Skills

CPU micro‑architecture RTL development Cache subsystem design Load‑store unit logic Front‑end quality checks Performance, power, area (PPA) optimization Team management Cross‑functional collaboration Verification coordination Physical design integration Technical leadership Project planning Mentoring Design documentation Problem solving Communication Agile hardware development (implied) Hardware description languages (Verilog, VHDL) EDA tools (Synopsys, Cadence) Timing analysis Design validation Strategic roadmap development

About Google

A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone. Check out our career opportunities at goo.gle/3DLEokh

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