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Physical Design Engineering, VP
Astera Labs đşđ¸ San Jose, California, United States of America
Lead end-to-end physical design execution for complex multi-die switching products and establish methodologies for chiplet architectures. Manage and mentor a growing team of engineers while collaborating across departments to meet performance, power, and area targets.
Responsibilities
- Lead end-to-end physical design execution for complex multi-die switching products and establish methodologies for chiplet architectures. Manage and mentor a growing team of engineers while collaborating across departments to meet performance, power, and area targets.
Requirements
- Requires a bachelor's degree in Electrical or Computer Engineering and 15+ years of experience in physical design of complex SoCs or ASICs. Proven track record in leading teams and delivering successful tapeouts in advanced process nodes is essential.
Benefits
- Discretionary bonus
- Incentives
- Benefits
Key Skills
About Astera Labs
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labsâ Intelligent Connectivity Platform integrates CXLÂŽ, Ethernet, NVLink⢠Fusion, PCIeÂŽ, and UALink⢠semiconductor-based technologies with the companyâs COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The companyâs custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
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