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ASIC and Logic Design Engineering Manager (Compute Test, North Reading)
Teradyne 🇺🇸 North Reading, MA 01864, United States of America
Lead a team of 4-6 engineers in designing and verifying FPGAs for next-generation compute test products. Manage project schedules, budgets, and staffing while collaborating across engineering disciplines to ensure product requirements are met.
Responsibilities
- Lead a team of 4-6 engineers in designing and verifying FPGAs for next-generation compute test products. Manage project schedules, budgets, and staffing while collaborating across engineering disciplines to ensure product requirements are met.
Requirements
- Requires a BSEE or MSEE with 12+ years of experience in digital FPGA design and at least 5 years of project leadership. Proficiency in RTL coding, simulation tools, and experience with AMD or Altera FPGAs is essential.
Benefits
- Medical Insurance
- Dental Insurance
- Vision Insurance
- Flexible Spending Accounts
- Retirement Savings Plans
- Life Insurance
- Disability Insurance
- Paid Vacation
- Paid Holidays
- Tuition Assistance Programs
Key Skills
About Teradyne
Teradyne brings high-quality innovations such as smart devices, life-saving medical equipment and data storage systems to market, faster. Its advanced test solutions for semiconductors, electronic systems, wireless devices and more ensure that products perform as they were designed. Its robotics offerings include collaborative and mobile robots that help manufacturers of all sizes improve productivity and lower costs.
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