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ASIC and Logic Design Engineering Manager (Compute Test, North Reading)
Teradyne 🇺🇸 North Reading, MA 01864, United States of America
The Logic Design Manager leads a team of 4-6 engineers in designing and verifying FPGAs for next-generation compute test products. This role involves project planning, resource management, cross-functional collaboration, and hands-on technical contributions to ensure successful product delivery.
Responsibilities
- The Logic Design Manager leads a team of 4-6 engineers in designing and verifying FPGAs for next-generation compute test products. This role involves project planning, resource management, cross-functional collaboration, and hands-on technical contributions to ensure successful product delivery.
Requirements
- Candidates must hold a BSEE or MSEE with at least 12 years of experience in digital FPGA design and integration. A minimum of 5 years in a project lead capacity is required, along with extensive proficiency in RTL coding, simulation tools, and hardware design standards.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- Flexible spending accounts
- Retirement savings plans
- Life insurance
- Disability insurance
- Paid vacation
- Paid holidays
- Tuition assistance
Key Skills
About Teradyne
Teradyne brings high-quality innovations such as smart devices, life-saving medical equipment and data storage systems to market, faster. Its advanced test solutions for semiconductors, electronic systems, wireless devices and more ensure that products perform as they were designed. Its robotics offerings include collaborative and mobile robots that help manufacturers of all sizes improve productivity and lower costs.
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