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Design Engineering Architect — Memory Modeling Portfolio
Cadence 🇰🇷 Seongnam-si, South Korea
Serve as the primary Korea-based expert for UFS/Unipro/MPHY/RMMI protocol stacks, providing technical leadership and debugging support for customers. Collaborate with the global R&D team to translate customer needs into product features and mentor junior design engineers.
Responsibilities
- Serve as the primary Korea-based expert for UFS/Unipro/MPHY/RMMI protocol stacks, providing technical leadership and debugging support for customers. Collaborate with the global R&D team to translate customer needs into product features and mentor junior design engineers.
Requirements
- Requires a Master's degree with 10+ years of experience or a PhD with 8+ years, specifically with deep expertise in the UFS/Unipro/MPHY/RMMI protocol stack. Proficiency in SystemVerilog/Verilog RTL and advanced English fluency are essential.
Key Skills
About Cadence
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
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