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Staff Engineer, VLSI Design Engineering (UVM, System Verilog) with 8 to 12 years of experience
Sandisk đŽđł Bengaluru, Karnataka, India
Lead the development of comprehensive test plans, verification strategies, and infrastructure for complex IP blocks and SoC designs. Collaborate with cross-functional teams to drive functional coverage-driven verification closure and perform root-cause analysis of design failures.
Responsibilities
- Lead the development of comprehensive test plans, verification strategies, and infrastructure for complex IP blocks and SoC designs. Collaborate with cross-functional teams to drive functional coverage-driven verification closure and perform root-cause analysis of design failures.
Requirements
- Requires 8 to 12 years of relevant experience in VLSI design and verification with a degree in ECE, VLSI, or Electrical Engineering. Candidates must possess advanced proficiency in UVM, SystemVerilog, and industry-standard verification tools.
Key Skills
About Sandisk
Sandisk is a leading developer, manufacturer and provider of data storage devices and solutions based on NAND flash technology. With a differentiated innovation engine driving advancements in storage and semiconductor technologies, our broad and ever-expanding portfolio delivers powerful flash storage solutions for AI workloads in datacenters, edge devices, and consumers. Our technologies enable everyone from students, gamers and home offices, to the largest enterprises and public clouds to produce, analyze, and store data. Our solutions include a broad range of solid state drives, embedded products, removable cards, and universal serial bus drives.
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