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The role involves designing and developing synthesizable RTL using Verilog and System Verilog based on architecture specifications. Responsibilities include collaborating with verification and physical design teams to ensure timing, power, and area requirements are met.
Responsibilities
- The role involves designing and developing synthesizable RTL using Verilog and System Verilog based on architecture specifications. Responsibilities include collaborating with verification and physical design teams to ensure timing, power, and area requirements are met.
Requirements
- Candidates must have strong expertise in digital design fundamentals, computer architecture, and AMBA protocols. A degree in Electrical or Computer Engineering and experience in ASIC/SoC design environments are required.
Key Skills
About Tessolve
Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3800+ employees worldwide, Tessolve provides a one-stop shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolve’s design services include solutions on advanced process nodes with a healthy ecosystem relationship with EDA, IP, and foundries. Our front-end design strengths, integrated with the knowledge from the backend flow, allow Tessolve to catch design flaws early in the cycle, thus reducing expensive re-design costs and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from
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