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Physical Design Engineering, VP
Astera Labs 🇺🇸 San Jose, California, United States of America
Lead the end-to-end physical design and implementation of complex multi-die switching products for AI infrastructure. Scale and mentor a world-class physical design organization while collaborating cross-functionally to meet performance, power, and area targets.
Responsibilities
- Lead the end-to-end physical design and implementation of complex multi-die switching products for AI infrastructure. Scale and mentor a world-class physical design organization while collaborating cross-functionally to meet performance, power, and area targets.
Requirements
- Requires a Bachelor's degree in Electrical or Computer Engineering and over 15 years of experience in physical design with a track record of successful tapeouts in advanced process nodes (7nm or below). Expertise in chiplet architectures, advanced packaging, and managing engineering teams of 20+ people is essential.
Key Skills
About Astera Labs
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink™ Fusion, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
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