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SSG Design Engineering Intern (Fall 2026)
Cadence đşđ¸ San Jose, California, United States of America
The Design Engineering Intern will work on Digital Design tasks or Design Verification tasks related to the Janus NoC IP product. This includes RTL implementation, simulation, debugging, and developing test plans.
Responsibilities
- The Design Engineering Intern will work on Digital Design tasks or Design Verification tasks related to the Janus NoC IP product. This includes RTL implementation, simulation, debugging, and developing test plans.
Requirements
- Candidates must be currently enrolled in a MS/BS program in Electrical Engineering, Computer Engineering, or a similar major. A deep understanding of Digital Design and/or Design Verification fundamentals is required, along with excellent automation skills.
Benefits
- Bonus
- Equity
- Benefits
Key Skills
About Cadence
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadenceâs Intelligent System Design⢠strategy, are essential for the worldâs leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the worldâs top 100 best-managed companies. Cadence solutions offer limitless opportunitiesâlearn more at www.cadence.com.
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