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Director, Silicon Design Engineering
Intel Corporation 🇺🇸 Santa Clara County, California, United States of America
Perform comprehensive timing analysis and optimization to ensure high-performance and power-efficient SoC designs. Collaborate with cross-functional teams to develop advanced clocking methodologies and validate timing constraints at the chip and block levels.
Responsibilities
- Perform comprehensive timing analysis and optimization to ensure high-performance and power-efficient SoC designs. Collaborate with cross-functional teams to develop advanced clocking methodologies and validate timing constraints at the chip and block levels.
Requirements
- Requires a degree in Electrical or Computer Engineering with 6 to 12+ years of experience depending on the degree level. Proficiency in static timing analysis, TCL scripting, and physical design tools and methodologies is essential.
Benefits
- Competitive Pay
- Stock Bonuses
- Health Insurance
- Retirement Programs
- Vacation
Key Skills
About Intel Corporation
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone. • Need help or have a support question? Visit Intel Support: http://ms.spr.ly/6054tmaop .
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