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Memory Interface PHY IP, Design Engineering Architect
Cadence đşđ¸ San Jose, California, United States of America
The Design Engineering Architect will contribute to PHY architecture development and drive architecture decisions aligned with standards and compliance requirements. They will also act as a customer-facing technical architect and collaborate with various teams to ensure architectural intent is implemented correctly.
Responsibilities
- The Design Engineering Architect will contribute to PHY architecture development and drive architecture decisions aligned with standards and compliance requirements. They will also act as a customer-facing technical architect and collaborate with various teams to ensure architectural intent is implemented correctly.
Requirements
- Candidates must have a Master's degree in Electrical Engineering or a related field and at least 15 years of industry experience in memory interface PHY or related domains. A strong background in JEDEC standards and excellent communication skills are also required.
Benefits
- Paid Vacation
- Paid Holidays
- 401k Plan With Employer Match
- Employee Stock Purchase Plan
- Medical Plan Options
- Dental Plan Options
- Vision Plan Options
Key Skills
About Cadence
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadenceâs Intelligent System Design⢠strategy, are essential for the worldâs leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the worldâs top 100 best-managed companies. Cadence solutions offer limitless opportunitiesâlearn more at www.cadence.com.
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