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Design Engineering Architect
Cadence đŽđł Bengaluru, Bangalore North, India
The role involves verification of Serial and Interface Design IPs and developing a robust UVM testbench. Additionally, it includes producing detailed verification strategies and test plans.
Responsibilities
- UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs
- Formal verification of complex design modules
- Participating in Emulation qualification of design IPs
- Understand design and produce detailed verification strategy and test plan
Requirements
- B. Tech/M.Tech with 18+ years of relevant experience
- Strong problem solving, analytical and debug skills
- Excellent verbal and written communications skills
- Ability to establish a close working relationship with both customer peers and management
Key Skills
About Cadence
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadenceâs Intelligent System Design⢠strategy, are essential for the worldâs leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the worldâs top 100 best-managed companies. Cadence solutions offer limitless opportunitiesâlearn more at www.cadence.com.
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