Staff Engineer, Digital design engineering

Develop and maintain FPGA prototyping platforms for ASIC designs, owning the complete FPGA build flow from RTL to implementation. Collaborate with various engineering teams to ensure seamless integration and continuous improvement of build infrastructure.

Responsibilities

• Develop and maintain FPGA prototyping platforms for ASIC designs
• Own the FPGA synthesis, implementation, and timing closure flow using Vivado
• Port ASIC RTL to FPGA: clock tree adaptation, memory model replacement, IP stub creation, constraint development
• Develop and maintain automated build scripts (TCL, Python) for compile ordering, file management, and normal/incremental Vivado builds
• Debug synthesis/implementation failures, resolve timing violations, and optimize QoR (clock skew, utilization, routing congestion)

Requirements

• 7+ years of FPGA design experience
• Expert-level Vivado experience (synthesis, implementation, timing constraints, incremental compile)
• Experience with ASIC-to-FPGA prototyping (RTL porting, memory replacement, clock adaptation)
• Deep understanding of FPGA clocking (MMCM, PLL, BUFG, BUFGCTRL, BUFGCE_DIV, clock muxing)
• Experience with timing closure on large designs (100K+ LUTs)
• Familiarity with XDC constraint development (clock definitions, false paths, multicycle paths, clock groups)

Key Skills