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Design Engineering Architect
Cadence Design Systems đŽđł Bengaluru, Bangalore North, India
Develop robust and scalable UVM testbenches to verify Serial and Interface Design IPs. Create detailed verification strategies and test plans while performing functional, formal, and emulation verification.
Responsibilities
- Verification role for Serial and Interface Design IPs verification
- UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs
- Formal verification of complex design modules
Requirements
- B.Tech/M.Tech with 18+ years of relevant experience
- Strong problem-solving, analytical and debug skills
- Excellent verbal and written communications skills
Key Skills
About Cadence Design Systems
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadenceâs Intelligent System Design⢠strategy, are essential for the worldâs leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the worldâs top 100 best-managed companies. Cadence solutions offer limitless opportunitiesâlearn more at www.cadence.com.
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