Staff Engineer, Digital design engineering

Develop and maintain FPGA-based prototyping platforms to enable early software development and RTL validation for complex SoC ASIC designs. Own the complete FPGA build flow, including synthesis, implementation, and timing closure using Vivado tooling.

Responsibilities

• Develop and maintain FPGA prototyping platforms for ASIC designs
• Own the FPGA synthesis, implementation, and timing closure flow using Vivado
• Port ASIC RTL to FPGA
• Develop and maintain automated build scripts
• Debug synthesis/implementation failures
• Collaborate with ASIC design teams
• Interface with FPGA vendor on tool issues

Requirements

• 7+ years of FPGA design experience
• Expert-level Vivado experience
• Experience with ASIC-to-FPGA prototyping
• Deep understanding of FPGA clocking
• Experience with timing closure on large designs
• Familiarity with XDC constraint development
• BS/BE in Electrical Engineering, Computer Science or Computer Engineering

Key Skills