Design Engineering Architect

Lead the design and development of high-speed Die-to-Die and SERDES products using leading-edge technology nodes. Collaborate with layout engineers and global technical teams to verify circuit blocks against customer specifications.

Responsibilities

• Design of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes
• Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications
• Work closely with Layout Design Engineers to design IC circuit blocks and PMA sections
• Work with Technical Team Leads in the areas of circuit design and SERDES architectures
• Work with global teams (US, west coast and east coast), which work in different time-zones

Requirements

• BEng, MEng, PhD or equivalent
• Minimum of 8 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design
• Good understanding of jitter and signal equalization techniques
• Design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators
• Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
• Proficiency in using CAD tools for circuit simulation, layout and physical verification

Benefits

• Opportunity to work with a global electronic design automation company
• Collaborative team environment
• Professional development opportunities

Key Skills