SMTS, IO/Clock Design Engineering

Responsible for the architecture, design, and verification of high-speed IO and clocking circuits for DRAM memory products. Focuses on optimizing bandwidth, reducing jitter, and collaborating with process integration teams for next-generation nodes.

Responsibilities

• Define, innovate, design, optimize, and verify high-speed IO and clocking circuits used in new DRAM products
• Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity
• Develop accurate modeling, analysis, and simulation methodology to capture key circuit performance metrics and their impact to product specifications
• Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities

Requirements

• Minimum MSEE + 10 years or BSEE + 12 years of industry experience
• Strong background in designing high-speed IO interface, timing, and clocking circuits with proven silicon successes
• Ability to supervise layout work and understand good layout practices for high-speed circuits to minimize parasitic impacts
• Strong communication skills with the ability to convey sophisticated technical concepts to other design peers both verbally and written

Benefits

• Choice of medical, dental, and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program and paid holidays

Key Skills