ASIC Design Engineering Technical Leader

Lead the architecture and micro-architecture of high-performance ASIC subsystems for next-generation data center silicon. Drive technical execution across design, verification, and physical implementation teams while mentoring engineers to improve design quality.

Responsibilities

• Drive the architecture and micro-architecture of high-performance ASIC subsystems for next-generation data center silicon
• Influence system architecture and key design decisions across complex SoC subsystems
• Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure
• Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets
• Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation

Requirements

• Bachelor's degree in Electrical or Computer engineering and 8+ years of ASIC experience
• Experience in high-performance RTL design using Verilog/SystemVerilog
• Experience with timing closure, power optimization, and clock gating techniques
• Strong debug, problem-solving, and cross-team collaboration skills

Benefits

• Medical, dental and vision insurance
• 401(k) plan with a Cisco matching contribution
• Paid parental leave, short and long-term disability coverage, and basic life insurance
• Opportunity to receive grants of Cisco restricted stock units

Key Skills