Staff Engineer, Digital Design Engineering

Lead the digital design execution from specification through physical implementation, focusing on RTL development and synthesis. Collaborate with DFT and physical design teams to ensure timing closure and deliver production-ready designs.

Responsibilities

• Lead RTL digital design for complex blocks and subsystems
• Execute full digital design flow including synthesis and static timing analysis
• Collaborate with DFT teams to integrate scan and test features
• Support place-and-route activities including timing closure and ECO implementation
• Partner with physical design teams to resolve layout-dependent timing and power issues
• Participate in design reviews and contribute to methodology improvements
• Document design specifications and implementation results

Requirements

• Strong expertise in digital circuit design and RTL development (Verilog/SystemVerilog)
• Solid understanding of digital design flows: synthesis, STA, and physical implementation
• Experience with synthesis using Cadence Genus
• Experience with place-and-route (physical layout design) using Cadence Innovus
• Working knowledge of DFT concepts and implementation tradeoffs
• Strong English written and verbal communication skills
• Ability to collaborate effectively across global, cross-functional teams

Benefits

• Opportunities to grow while contributing to technologies that shape the future of the intelligent edge
• Continuous learning and collaboration with world-class engineers
• Beneficial programs, aligned goals, and practices that create a more sustainable future

Key Skills