Short Term 2026 Hardware Design Engineering Intern/Co-Op

Collaborate on physical design verification and implementation for ASICs, focusing on memory interfaces and chip-to-chip interconnects. Perform RTL design, synthesis, floor planning, and timing closure to deliver high-end Machine Intelligence products.

Responsibilities

• Collaboration with Design Engineers on physical design verification and physical implementation for some of AMD's ASIC
• Work on memory interface simulation, discrete and embedded hardware products, and chip-to-chip interconnect
• Active participation in RTL design in Verilog, synthesis with timing-driven placement and design for power (DFP)
• Floor planning, power distribution, clock distribution, block/chip place and route, EM/IR analysis, timing closure, static timing analysis

Requirements

• Currently enrolled in a Canada-based university in a Bachelor's degree program majoring in Electrical Engineering or Computer Engineering or a related field
• Experience with semiconductor device physics, digital/logic circuits, and VLSI
• Knowledge of Verilog or VHDL hardware description languages
• Exposure to UVM methodologies
• Scripting languages such as Python, Perl, TCL, Ruby, Shell/UNIX scripting, C/C++, MATLAB
• Interest or experience in Machine Learning ASIC design

Benefits

• Opportunity to work on important projects that impact millions of end-users worldwide
• Gain real-world experience and expand your network
• Learn new skills and work alongside industry pioneers

Key Skills