Senior Technologist, Mask Design Engineering ((Extensive IC Layout Design-22 years of expertise in custom/AMS across analog, digital, and mixed-signal domain)

Lead the development and optimization of advanced mask layouts for next-generation memory technologies across analog, digital, and mixed-signal domains. Perform design verification, including DRC and LVS, and implement full-chip power distribution and floorplanning strategies.

Responsibilities

• Develop and optimize peripheral and core circuit layouts for Analog, Digital, and Mixed-signal domains
• Perform DRC (Design Rule Check) and LVS (Layout Versus Schematic) verification, parasitic extraction, and sign-off methodologies to guarantee design integrity and first-pass success
• Analyze and implement full-chip power distribution strategies and floorplanning optimization to ensure efficient electrical performance, minimize parasitics, and reduce die size
• Work closely with design and process engineering teams across multiple sites to resolve issues, align methodologies, and drive project success while maintaining high standards of accuracy and consistency

Requirements

• Over 22 years of proven expertise in custom full-chip layouts across analog, digital, and mixed-signal domains
• Highly skilled in industry-standard layout verification tools (DRC/LVS, parasitic extraction, and sign-off methodologies)
• Strong background in floorplanning strategies and placement optimization to minimize parasitics and reduce die size using a correct-by-construction approach
• Adept at working with multi-site, cross-disciplinary teams and managing small teams to drive project success
• Strong verbal and written communication skills with knowledge of layout automation techniques and a proactive mindset toward continuous improvement and efficiency

Benefits

• Opportunities to applicants with disabilities
• Inclusive environment where every individual can thrive through a sense of belonging, respect and contribution

Key Skills