Engineer, System Design Engineering

The role involves developing, integrating, and debugging Verification IP (VIP) for industry-standard protocols like PCIe, utilizing tools such as Siemens Questa for simulation and configuration of Avery VIPs for various environment levels. Responsibilities also include building SystemVerilog/UVM testbenches, analyzing coverage, debugging failures, and collaborating with RTL designers to resolve functional issues.

Responsibilities

• Develop, integrate, and debug Verification IP (VIP) for industry-standard protocols (e.g., PCIe or similar)
• Perform VIP-based simulation using Siemens Questa / Questa Advanced Simulator
• Configure, customize, and maintain Avery VIPs (or equivalent) for block-level, subsystem, and SoC-level environments
• Build and maintain SystemVerilog / UVM testbenches
• Analyze functional coverage, assertions, and protocol compliance results

Requirements

• Strong hands-on experience with VIP-based verification
• Proven expertise in Siemens Questa (debug, coverage, assertions, performance tuning)
• Experience using Avery VIP (or equivalent VIPs such as Synopsys VCS VIP, Cadence VIP)
• Solid understanding of SystemVerilog and UVM
• Good knowledge of SoC verification flows
• Experience debugging protocol-level issues in simulation

Benefits

• Opportunities to applicants with disabilities
• Inclusive environment where every individual can thrive through a sense of belonging, respect and contribution

Key Skills