Intern - Design Engineering
Cadence Design Systems200070 China, Shanghai, Dayangqiao, Shanghai Railway Station South Square
The intern will focus on high-speed digital DDR and HBM IP physical implementation, including developing necessary scripts or tools to enhance the current Physical Design (PD) flow. Responsibilities also involve completing project tasks, solving design issues, providing flow checks to avoid recurrence, and summarizing PPA optimization methodologies and results.
Responsibilities
- Focus on high-speed digital DDR and HBM IP physical implementation
- Develop necessary scripts or tools to enhance current PD design flow
- Work in product projects to complete project tasks and solve design issues
- Analyze and summarize PPA optimization methodologies and results
- Implement optimal design parameters and flows for different projects
Requirements
- Master's degree or above in microelectronics, electronic engineering, or other relevant field
- Strong problem-solving and team collaboration skills
- Fluent in English and Chinese
- Familiarity with digital backend tools
- Experience with high-speed digital design and physical implementation
Key Skills
About Cadence Design Systems
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
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