Manager, Die Design Engineering - APTD

This role involves leading, mentoring, and growing a team of die build and layout engineers, defining team goals, and owning the end-to-end die design and layout strategy for HBM die programs from concept through validation. Key technical duties include defining TSV placement strategy, overseeing micro-bump array design, and ensuring die design supports advanced packaging processes like TCB bonding.

Responsibilities

• Lead, mentor, and grow a team of die build and layout engineers across multiple experience levels
• Define team goals, individual development plans, and performance expectations aligned with program breakthroughs
• Build team capability in advanced packaging-aware layout techniques, 3D integration design rules, and DFT-aware layout
• Own the end-to-end die design and layout strategy for HBM die programs, from concept through tape-out and post-silicon validation
• Define die floorplanning strategy including TSV grid placement, micro-bump array layout, power domain partitioning, and KOZ management

Requirements

• Masters or PhD degree in Electrical Engineering, Computer Engineering, or related field required
• 10+ years of experience in die design and physical layout engineering
• 5+ years in a lead or management role overseeing layout engineering teams
• Direct hands-on experience with HBM, 3D-IC, or advanced packaging programs (CoWoS, SoIC, FOVEROS, or equivalent)
• Proven experience with TSV-based die design including KOZ management, micro-bump layout, and backside RDL

Benefits

• Opportunity to work on cutting-edge technology and contribute to the development of innovative memory and storage solutions
• Collaborative and dynamic work environment
• Professional development and growth opportunities
• Comprehensive benefits package

Key Skills