Sr. Manager Silicon Design Engineering

The manager will lead and mentor a team of design verification engineers, defining and driving the verification strategy for AMD's DFT IP to ensure first-pass silicon success for next-generation products. This includes overseeing test plan execution, ensuring coverage closure, and collaborating with cross-functional teams to resolve technical issues.

Responsibilities

• Lead and manage a team of design verification engineers, providing technical direction, mentorship, and performance feedback
• Define and drive verification strategy for DFT IP, ensuring alignment with architectural goals, schedule, and quality targets
• Oversee test plan creation, review, and execution for block- and system-level verification
• Ensure functional and code coverage closure, and track verification quality metrics for all deliverables
• Collaborate with design, architecture, and performance engineering teams to resolve complex technical issues and optimize verification approaches

Requirements

• Proven track record of leading ASIC or SoC design verification teams through successful product tape-outs
• Strong expertise in SystemVerilog, UVM, and coverage-driven verification methodologies
• Deep understanding of computer architecture, digital logic design
• Hands-on experience with EDA tools (Synopsys VCS, Cadence Xcelium, Mentor Questa)
• Debugging and problem-solving skills for complex, multi-clock domain designs
• Strong people management and communication skills to lead geographically distributed teams
• Bachelor’s or Master’s degree in electrical engineering, Computer Engineering, or a related field preferred

Benefits

• AMD benefits at a glance
• Diversity and Inclusion
• Equal opportunity, inclusive employers

Key Skills