ASIC and Logic Design Engineering Manager (Teradyne, North Reading)

The Logic Design Manager will lead a team of 4-6 engineers in designing and verifying FPGAs for next-generation products, requiring close collaboration with other engineering disciplines. This involves leading multiple simultaneous development projects, managing schedules, budgets, staffing, and contributing to RTL code implementation when necessary.

Responsibilities

• Lead multiple simultaneous FPGA or digital IP development projects
• Plan and track project schedule and budget
• Manage project staffing levels including both full-time and contract resources
• Represent the FPGA team on project core teams and at program reviews

Requirements

• BSEE or MSEE and 12+ years of relevant experience in Digital FPGA design and integration
• Minimum of 5 years of experience as an FPGA/ASIC project lead
• Extensive experience coding RTL (Verilog preferred)
• Extensive experience using digital simulation tools (Cadence preferred)

Benefits

• Base salary range: $155,500 - $248,700
• Discretionary bonus(es) based on financial performance
• Robust health and well-being benefit programs

Key Skills