Staff Engineer, Digital Design Engineering

This role involves providing technical leadership and mentorship to digital design engineers across various domains like CDC, low-power design, and timing closure, while architecting and designing key digital blocks in Verilog/SystemVerilog. The lead will also drive the adoption of AI tools, manage complex interface expertise, and establish IP-centric design management infrastructure.

Responsibilities

• Provide technical leadership and mentorship to digital design engineers across CDC, low-power design, synthesis and timing closure, DFT improvements, and silicon debug
• Architect and design key digital blocks (accelerators, datapath IPs) in Verilog/SystemVerilog with configurability to optimize Power, Performance, and Area (PPA)
• Demonstrate deep understanding of heterogeneous processor subsystems (A55, M55, M4, U55, RISC-V, DSP) and supporting infrastructure including caches, interconnects, GIC, DMA, MMU, CoreSight debug/trace, TZC, SMPU, and SPU

Requirements

• Minimum B.E. /B. Tech degree in Electrical/Electronics/Computer science
• 12+ years of relevant experience with a strong focus on definition/ architecture/ u-arch/ design and hands-on RTL coding experience using Verilog and System-Verilog
• Strong understanding of all aspects of ASIC/SoC product development incl Design Verification/ timing constraints/ closure, physical implementation, quality assurance flows with hands-on prior experience in a few of these aspects
• Proven experience in managing/ handling large complex hardware projects in lead role
• Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions

Benefits

• Employees have access to beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future

Key Skills