Design Engineering Architect

This senior technical leadership role involves defining the long-term verification architecture and methodology strategy for next-generation Tensilica CPU cores, ensuring functional integrity across multiple processor variants. Key duties include architecting simulation testbenches, leading UVM environment development, and championing advanced verification techniques like formal verification.

Responsibilities

• Define and own the long-term DV architecture, focusing on scalability across multiple processor variants and generations
• Architect simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments
• Champion the integration of formal verification, and AI-driven coverage analysis
• Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements
• Provide technical direction and set the standard for quality and metric-driven verification (MDV) across global teams

Requirements

• B.Tech/M.Tech in ECE with 10+ years of experience in SoC/CPU/DSP verification
• Deep expertise in SystemVerilog/UVM and C/C++ for architectural modeling
• Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe
• Expertise in scripting (Perl, Python, or Tcl) for verification flow automation

Benefits

• Equal employment opportunity (EEO) to all persons regardless of age, color, national origin, citizenship status, physical or mental disability, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, genetic information, marital status, status with regard to public assistance, veteran status, or any other characteristic protected by federal, state or local law

Key Skills