Staff Engineer, VLSI Design Engineering (SOC, Verification, UVM)

The Staff Engineer will develop test plans and verification infrastructure for complex IP/Sub-Systems and lead major deliverables for SoCs. They will also create a verification environment using UVM methodology and drive functional coverage driven verification closure.

Responsibilities

• Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC
• Create verification environment using UVM methodology
• Hands on in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure
• Create reusable bus functional models, monitors, checkers and scoreboards
• Drive functional coverage driven verification closure
• Work with architects, designers, and post-silicon teams

Requirements

• 5 to 7 years of relevant experience
• B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering
• Proficiency in Computer Science fundamentals
• Basic knowledge of c, c++, SystemC, perl, python, tcl, shell
• Unit/Sub-system/SOC level verification experience
• Exposure to industry standard verification tools for simulation and debug

Key Skills

• Proficiency in Computer Science fundamentals
• Basic knowledge of c, c++, SystemC, perl, python, tcl, shell
• Unit/Sub-system/SOC level verification experience
• Exposure to industry standard verification tools for simulation and debug
• Good debugging and problem solving skills
• Good communication skills and ability, desire to work as a team player

Benefits

• Opportunities to applicants with disabilities
• Inclusive environment where every individual can thrive through a sense of belonging, respect and contribution