Principal Engineer, VLSI Design Engineering

The Principal Engineer will be responsible for the Logic design development and ownership of the RTL modules for 3D NAND flash memory. This includes driving design activities, ensuring timing closure, and collaborating with cross-functional teams.

Responsibilities

• Understanding the NAND architecture and collaborating with other Core/Analog design groups
• Driving the design activities and responsible for design of the RTL modules
• Timing Closure of the Logic modules
• Creating the SVA check specs
• Working with verification team on the creating and updating test plans
• Working with cross-functional teams on implementing the new modes
• Working with the BUs to come up with the effective solution based on customer requirements
• Developing the verification for the new modes implemented
• Simulating and debugging the RTL using the industry standard tools

Requirements

• Experience of 8-12 years in SOC/ASIC development
• Knowledge of NAND flash technology is an added advantage
• Bachelor's/Master's degree in the Electrical Engineering/Microelectronics
• Should have contributed in the Design for at least 1 taped-out project
• Proficient in Verilog language and RTL design
• Proficient in Timing Analysis
• Expertise in Clock Domain Crossing(CDC) and RDC

Key Skills

• Verilog language and RTL design
• Timing Analysis
• Clock Domain Crossing(CDC) and RDC
• Detail-oriented candidate who can work with cross-functional teams and the verification teams
• Strong problem-solving skills
• Excellent communication written, oral and presentation skills
• Leadership skills to drive the innovation activities with the team