Senior Manager Silicon Design Engineering

Lead a Silicon Engineering group to innovate with internal teams and external partners. Collaborate with architecture, physical design, and product engineers to achieve first pass silicon success.

Responsibilities

• A strong leader with experience working with a distributed engineering team
• Strong mentoring and coaching skills
• Collaborate with multi-functional leaders to drive AMD's success
• Design of IP and subsystems with integration of AMD and other 3rd party IPs

Requirements

• 12-15 years full-time experience in IP hardware design
• Proven experience managing and leading engineering teams
• Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
• Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
• Clock domain crossing (CDC) tools

Key Skills

• Verilog/SystemVerilog RTL logic design of high-speed, multi-clock digital designs
• Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
• Clock domain crossing (CDC) tools
• SoC design flows
• IP/SS/SoC Power Management techniques – Power Gating, Clock Gating

Benefits

• AMD benefits at a glance