Staff Engineer, VLSI Design Engineering (SOC Verification, System Verilog, UVM)

The engineer will develop synthesizable RTL models and validate them using UVM testbenches. This role is essential for pre-silicon validation and accelerating software bring-up for complex SoCs.

Responsibilities

• Develop clean, synthesizable RTL models for IP blocks and subsystems using Verilog/SystemVerilog
• Collaborate with design teams to ensure RTL is emulation-friendly and meets performance and debug requirements
• Create and maintain UVM-based testbenches to validate RTL functionality and coverage
• Debug RTL and testbench issues using simulation and emulation tools
• Package and deliver validated RTL models to the emulation team, including synthesis scripts, configuration files, and documentation

Requirements

• 4 to 7 years of experience in RTL design, UVM validation, and emulation support
• Bachelors/Masters from a reputed College/University with Electronics and communication/Embedded Systems background
• Strong Problem Solving and Debug skills
• Efficient Communication
• Tools/Languages: Verilog, SystemVerilog, UVM

Key Skills

• Verilog/SystemVerilog RTL coding and digital design fundamentals
• UVM methodology and testbench development
• Emulation platforms (e.g., Cadence Palladium, Protium, Synopsys ZeBu, Mentor Veloce)
• Simulation tools (e.g., VCS, Questa, Xcelium) and waveform debug
• Scripting skills in Python, TCL, or Perl for automation and testbench control