Staff Engineer, Physical Design Engineering

The role involves leading timing sign-off and closure for complex mixed-signal SoCs, ensuring designs meet timing, signal integrity, and reliability requirements. Responsibilities include performing full-chip and block-level STA, analyzing setup and hold issues, and collaborating with various teams to meet timing requirements.

Responsibilities

• Perform full-chip and block-level STA for multiple modes and corners
• Analyze and resolve setup, hold, and clock domain crossing (CDC) issues
• Create and validate timing constraints (SDC) for synthesis and P&R flows
• Execute timing sign-off using industry-standard tools (e.g., PrimeTime, Tempus)
• Implement ECOs for timing fixes and validate changes
• Collaborate with RTL, physical design, and DFT teams to ensure timing requirements are met
• Develop automation scripts (TCL, Python, Perl) to streamline STA tasks and improve efficiency

Requirements

• B.Tech/M.Tech in Electrical/Electronics Engineering
• 9–12 years in STA and physical design implementation for high-speed SoCs on advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm)
• Strong expertise in Static Timing Analysis, constraint development, and sign-off
• Ability to innovate flows to meet QoR targets and ensure predictability
• Good understanding of device/interconnect and circuit aspects of UDSM technologies
• Proficiency in TCL, Python, or other scripting languages

Key Skills

• Strong expertise in Static Timing Analysis, constraint development, and sign-off
• Ability to innovate flows to meet QoR targets and ensure predictability
• Good understanding of device/interconnect and circuit aspects of UDSM technologies
• Proficiency in TCL, Python, or other scripting languages