Principal Engineer, VLSI Design Engineering

The individual will be responsible for Logic design development and ownership of the RTL modules. They will drive design activities and collaborate with other design groups to ensure effective solutions based on customer requirements.

Responsibilities

• Understand the NAND architecture and collaborate with other Core/Analog design groups
• Drive the design activities and responsible for design of the RTL modules
• Timing Closure of the Logic modules
• Create the SVA check specs
• Work with verification team on the creating and updating test plans
• Work with the cross-functional teams on implementing the new modes
• Work with the BUs to come up with the effective solution based on customer requirements
• Develop the verification for the new modes implemented
• Simulate and debug the RTL using the industry standard tools

Requirements

• Experience of 9-12 years in SOC/ASIC development
• Knowledge of NAND flash technology is an added advantage
• Bachelor's/Master's degree in the Electrical Engineering/Microelectronics
• Contributed in the Design for at least 1 taped-out project
• Proficient in Verilog language and RTL design
• Proficient in Timing Analysis
• Expertise in Clock Domain Crossing(CDC) and RDC

Key Skills

• Verilog language
• RTL design
• Timing Analysis
• Clock Domain Crossing(CDC) and RDC
• Strong problem-solving skills
• Excellent communication written, oral and presentation skills
• Leadership skills

Benefits

• Sandisk thrives on the power and potential of diversity
• Committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution